EM250
SC1_UARTFRAC [0x44B6]
15
0-R
0
0
0-R
7
14
0-R
0
0
0-R
6
13
0-R
0
0
0-R
5
12
0-R
0
0
0-R
4
11
0-R
0
0
0-R
3
10
0-R
0
0
0-R
2
9
0-R
0
0
0-R
1
8
0-R
0
SC1_UARTFRAC
0-RW
0
SC1_UARTFRAC
[0]
The baud rate fractional remainder (F) of the clock rate as derived from the equation: rate =
24MHz / ( 2 * ( N + (0.5*F) ) )
SC1_UARTCFG [0x44AE]
15
0-R
0
0
0-R
7
14
0-R
0
SC1_UARTAUTO
0-RW
6
13
0-R
0
SC1_UARTFLOW
0-RW
5
12
0-R
0
SC1_UARTODD
0-RW
4
11
0-R
0
SC1_UARTPAR
0-RW
3
10
0-R
0
SC1_UART2STP
0-RW
2
9
0-R
0
SC1_UART8BIT
0-RW
1
8
0-R
0
SC1_UARTRTS
0-RW
0
SC1_UARTAUTO
SC1_UARTFLOW
SC1_UARTODD
SC1_UARTPAR
SC1_UART2STP
SC1_UART8BIT
SC1_UARTRTS
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Set this bit to enable automatic nRTS assertion by hardware. nRTS will be deasserted when
the UART can receive only one more character before the buffer is full. nRTS will be
reasserted when the UART can receive more than one character before the buffer is full. The
SC1_UARTRTS bit in this register has no effect when this bit is set.
Set this bit to enable nRTS/nCTS signals. Clear this bit to disable the signals. When this bit is
cleared, the nCTS signal is asserted in hardware to enable the UART transmitter. The
GPIO_CFG register should be configured for mode SC1-4A for hardware handshake with
nRTS/nCTS and SC1-2 for no handshaking.
Clear this bit for even parity. Set this bit for odd parity.
Clear this bit for no parity. Set this bit for one parity bit.
Clear this bit for one stop bit. Set this bit for two stop bits
Clear this bit for seven data bits. Set this bit for eight data bits.
nRTS is an output signal. When this bit is set, the signal is asserted (== TTL logic 0, GPIO is
low, 'XON', RS232 positive voltage), the transmission will proceed. When this bit is cleared,
the signal is deasserted (== TTL logic 1, GPIO is high, 'XOFF', RS232 negative voltage), the
transmission is inhibited.
Page 49
120-0082-000V Rev 1.1
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